This invention is in the field of logic timing analysis, and particularly concerns the problem in logic circuit timing analysis of adjusting a path delay to account for the effect of phase differences between clock signals which drive data signals on the path.
In static timing analysis, the logic design of a circuit is analyzed to identify timing problems in the design. The logic design is analyzed by propagating cumulative path delays from the inputs of the circuit to its outputs in a single pass. A timing problem arises at a point in the circuit which joins two circuit paths when the signal along one of the paths arrives at the point with an improper timing relationship to the signal along the second path.
Static timing analysis, therefore, concerns a point-by-point analysis of a logic circuit in which all possible paths to the current point are analyzed to detect timing problems. This is contrasted with dynamic timing analysis in which logic circuit operation is simulated. One example of static timing analysis is found in U.S. Pat. No. 4,263,651, which is commonly assigned with this application.
Static timing analysis proceeds by propagating maximum delays from the inputs to the outputs of a design in a single pass through the design. Assuming that the design includes clocked elements such as latches, the single-pass analysis means that such elements would be clocked only once during the analysis. If data is generated at the output pin of the clocked element (the "source" element) later than it is expected to be clocked into the input pin of the next downstream clocked element (the "sink" element), the data will appear to be too late from the standpoint of the sink latch. This anomaly is resolved by making a timing adjustment to the delay value which is propagated out of the output pin of the source latch. The timing adjustment is made by subtracting a clock cycle from the delay value so that the data will appear to have been clocked out of the output pin during the clock cycle preceding that during which it is clocked into the downstream input pin.
An example of the timing adjustment problem is illustrated in FIG. 1. FIG. 1 illustrates how delay adjustments are made according to prior art static timing analysis methods. FIG. 1 illustrates a logic circuit design consisting of a plurality of circuit elements, called "blocks". Each block represents a particular kind of logic element and includes one or more input ports on its left-hand side and one or more output ports on its right-hand side. In FIG. 1, two distinct kinds of circuit elements are illustrated. Blocks (BLKS) 1, 2, 3, and 5 are clocked circuit elements called latches. Each latch consists of two elements, one including a data input pin D0, a clock input pin C0, and an output pin 10. The second element has a data input internally connected to the first element and uses the B0 input pin for clocking into the second element. Each latch is fed a clock signal consisting of two clock waveforms. Data presented to the D0 input enters the first element while the clock input to the C0 input pin has a positive level. The data is latched or retained in the first element at the rising edge of the clock input to the C0 pin. The data in the second element is thus available as the output at the next rising edge of the clock waveform at the B0 input pin.
Block 4 is representative of non-clocked combinatorial logic elements such as gates, inverters, and the like. In FIG. 1, block 4 represents an AND gate with two input pins A0 and A1 and a single output pin 10.
In the logic design of FIG. 1, any block whose output is provided to an input of another block in the design is termed a "source" block. Any input pin in the logic design of FIG. 1 which does not receive a signal from a source block in the logic design is termed a "primary" input, while the output of any block in the logic design which is not connected to the input of another block in the same logic design is termed a "primary" output.
The logic design of FIG. 1 employs multiple-phase system clocking in which the operations of clocked elements are controlled by a plurality of clock signals. These clock signals are illustrated in FIG. 2, and are interlaced in that all the clock signals have the same frequency, but separate respective phases. FIG. 2 illustrates four clocks T0, T1, T2, and T3. One system clock cycle of the logic design of FIG. 1 comprises an interlaced sequence of four staggered clock pulses, one from each of the respective clock signals T0-T3. The cycle length is 100 timing units; each clock signal has a pulse width of 20 timing units from rising to falling edge; and the falling edge of each clock signal is separated from the rising edge of the next clock signal by five timing units.
Returning to the description of timing adjustment according to prior art static timing analysis in FIG. 1, a goal of the procedure is to determine, for example, whether any timing problems exist between a data signal input to the input pin D0 of block 3 and the T1 clock input to the C0 input of the block. The analysis regards the arrival time of a signal produced from the output pin of block 4 with respect to the occurrence of the rising edge of the T1 clock. If the arrival time of the data signal precedes the rising edge of the T1 clock, the signal will be latched; otherwise, the rising edge of the T1 will latch an incorrect signal into the block. The output pin of block 4 produces the signal in response to signals produced by block 1 and block 2. Each of these signals has respective delay characteristics, and either can affect the output of block 4. Therefore, the timing analysis with respect to block 3 must take into consideration the fact that the output of block 4 can change at different times, depending upon the outputs of blocks 1 and 2.
As should be evident from the foregoing discussion, static timing analysis operates by tracing back the paths through the logic design from a point where the analysis is being conducted. Thus, if analysis is being conducted at the input of block 3, static timing analysis traces back the paths which feed input pin D0. The paths are rearwardly traced to those primary inputs which ultimately drive the pin of interest. In FIG. 1, T0 and T2 are the primary inputs which affect the signal input to pin D0 in block 3.
In prior art static timing analysis, once the primary inputs are identified, the paths beginning with those primary inputs are traced forward to the point of interest in the logic design while delay values are accumulated along the paths. In this regard, the number in parentheses in FIG. 1 represent the delay values that would be calculated by a static timing analysis program of the prior art. Consider, for example, the path from block 1 to block 3. The data is clocked out of block 1 by the clock T0 at time zero, with a delay through block 1 of five timing units. This delay value is denoted as (5) on the signal path connecting output pin 30 of block 1 to input pin A0 of block 4. Assuming a delay of two timing units through block 4, the total delay from block 1 to the data input pin of block 3 is 7 timing units.
Consider now the accumulated delay from block 2 to block 3. Output pin 30 of block 2 is clocked by the rising edge of clock T2, which is delayed by 50 timing units with respect to the beginning of a system clock cycle. Assuming delays of 5 timing units through block 2 and 2 timing units through block 4, a signal originating at block 2 will arrive at input pin D0 of block 3 with a delay of 62 timing units. Thus, data clocked out of block 2 by the clock T2 at time 50 will arrive at the input pin D0 of block 3 at time 62. Apparently, data is clocked out of block 2 later than it is expected to be clocked into block 3 by the rising edge of T1. Manifestly, the designer intends that data from the previous cycle of blocks is to be clocked into block 3. This intent is implemented by specifying an adjust value of -100 for the path from block 2 to block 3, which retards the delay value by one system clock cycle. The delay value will be denoted as (-43 ). In static timing analysis as presently practiced, this adjust value cannot simply placed at the input pin of block 3, because this would cause the path from block 1 to block 3 to be incorrectly adjusted. Therefore, it is necessary to follow the paths back from block 3 to the point at which they diverge to correctly place the adjust value. The correct placement of the adjust value is at A1 input to block 4 as illustrated in FIG. 1.
In a logic design with multi-phase clocks, many clocked elements, and many signal paths determining where an adjust value should be placed for static timing analysis is a difficult task. The adjust value must be placed so that the paths requiring an adjustment are adjusted, without affecting the paths not requiring adjustment. In fact, it may be the case in a logic configuration that an adjustment cannot be properly made because of conflicting adjust values. For example, consider block 5 in FIG. 1 where an adjust value is required at the A1 input to block 4 for the path from block 2 to block 3 as in the first example. However, the path from block 2 to block 5 does not require an adjust value because the data is clocked out of block 2 before being clocked into block 5. The requirement to adjust the delay value for the path from block 2 to block 3 does not apply to the path from block 2 to block 5. In this case, it is not possible to correctly analyze both paths in a single timing analysis run using previous static timing analysis tools.
The examples discussed with reference to FIG. 1 illustrate that generation of timing adjustments according to previous static timing analysis tools can be a complex, and potentially insoluble, problem. To set up timing adjustments required by previous static timing analysis tools, the designer must identify those paths requiring an adjustment, determine where along the path the adjust value can be placed so that other paths will be not incorrectly adjusted, and resolve any conflicting adjust values. This becomes more difficult as the amount of logic being analyzed increases. In addition to requiring a significant amount of effort, the prior art generation of timing adjustments is inconsistent and error prone and an incorrect set of timing adjust values can potentially hide an actual timing problem.